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Flexibilis Ethernet Switch (FES)
FES is a triple-speed (10Mbps/100Mbps/1Gbps) Ethernet Layer 2 switch IP with gigabit forwarding capacity per port. FES is compatible with IEEEv2 end-to-end transparent clock functionality, which significantly improves the ability to fight degradation of clock information quality in large networks.
FES standard features include:
- 10/100/1000 Mbit/s Full-Duplex Ethernet interfaces (IEEE 802.3x)
- Compatible with IEEE standard 802.1D Media Access Control (MAC) Bridges
- Ethernet packet forwarding at wire-speed, non-blocking
- Media Independent Interfaces (MII) and Gigabit Media Independent Interfaces (GMII) for attaching to external Physical Layer devices (PHY) and host system CPU. Other interface types including SGMII, RGMII, RMII, 1000BASE-X and 100BASE-FX can be provided with optional interface adapters on the FPGA
- Avalon slave interface for register access
- PTPv2 end-to-end one-step transparent clock processing at hardware
- PTPv2 peer-to-peer transparent clock support functions
- PTPv2 boundary and ordinary clock support functions
- Ethernet packet filtering and prioritization on each of the ports
- Virtual LAN tagging and priority tagging
FES with only the standard features is available in several different configurations, from 3-port to 12-port. All of the ports can be either copper or fiber Ethernet interfaces, or connected to other FPGA blocks. FPGA resource usage varies from about 14,500 FPGA registers (3-port) to about 58,000 FPGA registers (12-port). Packet forwarding takes place at wire-speed, and the switching operation is non-blocking.
FES has an Avalon interface for register access. The registers can also be accessed by other methods like MDIO and I2C by using separate adapters. The host CPU can be used to manage the functionality of FES or to implement the Spanning Tree Protocol (STP) or Rapid Spanning Tree Protocol (RSTP). The CPU port can be configured as a management port which enables the CPU to be able to send and receive any kinds of Ethernet frames to/from any other port.
Multi-Gigabit Forwarding Engine
The core of FES is a multi-gigabit forwarding engine capable of serving up to twelve full-duplex gigabit Ethernet ports, thus forwarding twelve gigabits of data every second. All the ports have four priority queues enabling four different priority levels. During a congestion situation frames are discarded in WRED (Weighted Random Early Detection) fashion, which drops frames from low priority queues first, preserving the more important streams even during congestion. Forwarding latency is minimal thanks to gigabit operation.
To preserve valuable FPGA internal memory resources the switch core includes advanced memory management functionality: frames are stored in a centralized manner and in fragments of 512 bytes. This prevents small frames from consuming the same amount of memory, as maximum sized frames. Also, not having a fixed size per port queue prevents the currently empty queues from allocating memory that could be used by the other queues. 512 kbits of FPGA internal memory is reserved for output queues, which makes it possible to queue 42 to 128 Ethernet frames, depending on their length.
Precision Time Protocol
The Precision Time Protocol (PTP), defined in IEEE standard 1588, enables precise synchronization of device clocks in packet based networks. Devices are automatically synchronized to the most accurate clock in the network. The protocol supports system wide synchronization accuracy, usually in sub microsecond range, with minimal network and local clock computing resources. The protocol is used in applications such as test and measurement, power-line management, industrial automation and telecom applications. FES implements an IEEE 1588 transparent clock between all of its input and output ports.
Read more about Precision Time Protocol (PTP)
FES also has several optional features:
- Compatible with IEC 62439-3 ”High-availability Seamless Redundancy (HSR)”
- Compatible with IEC 62439-3 ”Parallel Redundancy Protocol (PRP)”
- Traffic shaping and policing
- Frame encryption and decryption with MACsec
FES with features for redundant communication is called Flexibilis Redundant Switch (FRS). FRS is targeted for applications requiring high availability.